1. Field of the Invention
The present invention relates to the methodologies and circuitry for arbitrating the use of a system bus in an integrated circuit multimaster digital system, and in particular relates to system bus arbiters and controllers dealing with an assigned priority or hierarchy of users.
2. Description of the Prior Art
The typical prior art microprocessor system was comprised of a microprocessor coupled to a control, address and data bus to which was coupled an addressable memory in an input/output device. The single microprocessor controlled all activity on the control, address and data bus and was the single master of the memory and input/output device. With the advent of accelerating price reductions in microprocessors the memory and input/output components became the most expensive components of the digital system. Therefore, higher order digital systems with greater capacities and complexities could be organized by coupling multiple central processors to a single control, address and data bus which shared common memory and input/output peripherals. However, in order to share the memory and input/output peripherals some means was required to resolve priority conflicts between among the multiple central processors. This entailed the addition of a priority resolving circuit which was coupled to the multiple central processing units by an arbitrating control bus having a plurality of bus request and status signals. A typical priority resolving circuit contained the entire logic for arbitration of the control, address and data bus among the multiple central processing units. Generally, the concentration of the arbitration circuit within a single priority resolving module entailed limitations both upon the practical complexity of the arbitration scheme as well as the number of central processing units which could be included within the system.
These prior art digital systems have been increasingly organized and configured about a multimaster bus. In other words, a single system bus will be shared by a number of intelligent processing units or bus masters, some of which may be general central processors and some of which may be specialized or dedicated processors, such as an input/output processor (IOP).
A bus master, such as a processor or a direct memory accessing circuit, is defined as a circuit which is capable of controlling an associated bus. Thus, a local bus master is a circuit which may control a local bus, and a system bus master is one which controls a system bus. The system bus is that bus through which a plurality of bus masters, usually intelligent processing circuits, share a common memory and input/output devices. A local bus is that bus through which one or more circuits or a processor's family may communicate with a plurality of dedicated circuits, including dedicated memories and input/output devices. Thus, by decentralizing the intelligence or decision making capability of the digital system among separate processors coupled to a common system bus, information may be manipulated and transferred in a plurality of overlapping or time-shared sequences to achieve highly sophisticated circuit operations at low unit pricing by sharing the costly common peripherals such as memory and input/output devices.
Therefore, some means must be devised for coordinating the access of the plurality of users to the shared system bus. Prior art bus arbitration has been based upon the concept that at any given time only one bus master or user will have priority over all the other masters or users coupled to the system bus. Such "one master at a time" schemes have used parallel priority resolving techniques, serial priority resolving techniques, and rotating priority resolving techniques.
The parallel priority resolving technique provides for a separate bus request line for each arbiter circuit coupled to the multimaster system bus. Each bus request line is coupled to a priority encoder which generates the priority address of the highest priority bus request line which is then active. The binary address is decoded by a decoder to select the corresponding bus priority request line (BPRN), which goes active to designate the highest priority requesting arbiter. The arbiter receiving this priority bus request signal then couples its associated local bus master to the multimaster system bus as soon as the system bus becomes available. When one bus arbiter gains priority over another arbiter, it cannot immediately seize the bus, but must wait until the present bus user completes its transfer cycle. Upon completing the transfer cycle, the present bus user recognizes that it no longer has priority and then surrenders the bus to the higher priority user. Once the higher priority user controls the bus, all other lower priority users are kept off.
The serial priority revolving technique eliminates the need for a priority encoder and decoder arrangement by combining the bus arbiters into a daisy chain organization. The higher priority bus arbiter's bus priority output terminal is coupled to the bus priority input terminal of the lower priority arbiter. Thus, the hierarchy of priorities is serially shifted downward as long as the higher priority arbiter is not then requesting access to the system bus.
The rotating priority revolving technique employs complex logic circuitry which rotates the priority assignments among the plurality of users such that each user, at some given time, is treated as the highest priority user.
Each of the prior art arbitration methodologies and circuitries are subject to disadvantages and inefficiencies in the use of the system bus. The rotating priority resolving technique requires ever increasing degrees of complexity as the number of users of the system bus increases. The serial priority bus arbiter is limited to a restricted number of users as determined by the comparative duration of the cumulative daisy chain propagation delays with respect to the duration of the system bus clock. The parallel priority resolving technique is subject to the defect that the system bus is captured by the highest priority user then active, keeping all other users off the system bus even during those times where the highest priority user is momentarily accessing another bus or has entered an idle state.
The present invention provides for a methodology and circuitry for bus arbitration which overcomes bus inefficiencies of the prior art priority resolving techniques.